1) Field of the Invention
This invention relates to a circuit designing apparatus, a circuit designing method and a timing distribution apparatus suitable for use for designing, for example, a large scale circuit.
2) Description of the Related Art
Generally, in order to design a circuit of a semiconductor chip (hereinafter referred to as semiconductor circuit) or an entire electronic apparatus such as a semiconductor device or a printed board or a component of an electronic apparatus or a subsystem (hereinafter referred to as system circuit), a designer (user) uses a technique called division design wherein the entire circuit is divided into two or more units and the individual units are designed independently of one another.
The unit signifies an element having a predetermined circuit function and is called circuit module or module. In the following description, in order to distinguish a unit before processed and a unit after processed, the unit before processed is referred to as unit to be processed or unit of a design object. Meanwhile, the unit after processed is referred to as processed unit.
A technique of designing a unit in a condition wherein it contains or includes another unit designed independently is called hierarchical design. The hierarchical design has a hierarchical characteristic in that the contained unit is hierarchically lower and the containing unit is hierarchically higher. Division circuit designed partially are finally aggregated into a single unit wherein the hierarchically highest layer is the entire circuit. In the following description, the term hierarchical design generally signifies division design.
FIG. 43 illustrates a concept of hierarchical design. Referring to FIG. 43, a semiconductor circuit (which may be hereinafter referred to as chip) 100 is a circuit of the hierarchically highest layer and contains a pair of circuit modules (a circuit module may be hereinafter referred to merely as module) 100x and 100y. The module 100x contains a pair of modules 101x and 102x, and the module 100y contains a pair of modules 101y and 102y. Further, the modules 101x and 101y contain modules 103x and 103y, respectively, and the modules 102x and 102y contain modules 104x and 104y, respectively. Thus, a designer can design the individual modules independently of one another, and this augments the design efficiency.
Since the circuit scale increases year by year, it is demanded for a circuit designing apparatus (which may be hereinafter referred to merely as designing apparatus) to have a capability of processing a greater amount of data.
On the other hand, to design an entire semiconductor circuit collectively without using hierarchical design is called collective design. The collective design is not applied to design of a circuit of a scale greater than a certain scale principally by reason of the hardware capacity of a designing apparatus, and the hierarchical design is used popularly.
In particular, a working memory is restricted in capacity and also in processing time. A designing apparatus uses a large working memory area for processing required due to change of a circuit and so forth. Processing for circuit change or the like is described with reference to FIGS. 44 to 46.
FIG. 44 is a block diagram of a semiconductor circuit designing apparatus. Referring to FIG. 44, the designing apparatus 500 shown is used to design a semiconductor circuit and includes an automatic design processing section 200 and a circuit information database 300. The circuit information database 300 stores information of circuit elements such as, for example, flip-flops and registers. The automatic design processing section 200 executes circuit designing and includes a hardware description language (HDL) conversion processing section 200a, a peculiarizing processing section 200b, a test circuit production processing section 200c, a load adjustment processing section 200d, and an HDL output processing section 200e. 
The HDL conversion processing section 200a HDL-converts an HDL source code (which may be hereinafter referred to simply as source code) to obtain a unit to be processed and stores the unit into the circuit information database 300. The peculiarizing processing section 200b allocates a name of a different module produced as a result of circuit change by the designer so that it may not overlap with any other name and makes intrinsic.
The test circuit production processing section 200c produces a test circuit and produces information such as a hierarchical layer name, a name of an additional terminal or an additional gate, and a connection order between modules. The load adjustment processing section 200d adjusts the load to a module and produces information such as a hierarchical layer name, an input terminal load, and a driving capacity of an output terminal. The HDL output processing section 200e causes a result of the processes performed in this manner to be reflected on the source code.
Where a plurality of circuits having the same function are required in designing of a large scale circuit, a technique called plural reference is used. The plural reference is a technique wherein a module having a necessary function is designed as a unit to be processed and a higher hierarchical layer refers to the unit to be processed by a plurality of times. Consequently, the designer can omit repetitive arrangement of a module, can load information regarding the same module into a working memory and can prevent redundancy in repeated calculation. It is to be noted that, in contrast to the plural reference, a unit which is referred to only once is called a unit of single reference. Now, peculiarizing is described with reference to FIGS. 45(a) and 45(b).
FIGS. 45(a) and 45(b) are diagrammatic views illustrating a peculiarizing process. A chip 150a shown in FIG. 45(a) is a circuit before peculiarizing and includes two modules 151 each having a module 151a (represented by A). Information of the modules 151a is written as a data image 154a (represented by A) in the circuit information database 300.
Meanwhile, a chip 150b shown in FIG. 45(b) is a circuit after peculiarizing and includes a module 151 and another module 152. The module 152 is obtained by peculiarizing of the module 151 and has a module 152a (represented by Axe2x80x2) duplicated from the contained module circuit. Information of the modules 151a and 152a is written as data images 154b (represented by A-0) and 154c (represented by A-1) in the circuit information database 300, respectively.
The chip 150a shown in FIG. 45(a) has a unit (for example, the module 151) plural-referred to within a certain period of a design step (which may be hereinafter referred to merely as step). The peculiarizing process signifies a process necessary for a designer to change a unit which is plural-referred to so that it may be placed into a state wherein it can be single-referred to as seen in FIG. 45(b) in the later process.
More particularly, the designer processes to duplicate a unit (module 151) by a number of times by which the unit has been referred to and change the names of the duplicates so as to change the module into units which are single-referred to. For example, in the example shown in FIG. 45(b), only one duplicate is produced. Upon such duplication, peculiar names A-0 and A-1 are allocated to the original module 151a and the duplicated module 152a, respectively, and consequently, the designer can distinguish the two modules from each other.
Further, in FIG. 44, the peculiarizing processing section 200b writes such changes in the individual steps into the circuit information database 300, thereby completing the peculiarizing process. Thereafter, the test circuit production processing section 200c and the load adjustment processing section 200d read out the contents changed by the peculiarizing process from the circuit information database 300, and produce a test circuit and adjust the load, respectively.
As a technique different from the hierarchical design and the collective design, ECO (Engineering Change Order) design is used frequently. The ECO design is a technique of changing only part of a unit to be processed while the other portion of the circuit remains not changed to re-design the unit. The hierarchical design can be applied to the ECO design.
The reason why the ECO design is used is that re-designing regarding only part of a semiconductor circuit decreases the processing time when compared with re-designing of the entire circuit.
FIGS. 46(a) to 46(c) are diagrammatic views illustrating the ECO design. A chip 250a shown in FIG. 46(a) is completed in design (which may be hereinafter referred to as ordinary design) once and is planned to be subject to the ECO design. A module 252a (represented by C) is a circuit element of a module 251a of the chip 250a. In other words, both of the module 251a and the module 252a have a test circuit and a clock circuit added thereto, and have been produced automatically by a designing apparatus. Further, the module 252a is written as a data image 260a (represented by C) in a circuit information database 300.
Meanwhile, the chip 250a shown in FIG. 46(b) is in a state before the ECO design is started. In the chip 250a shown in FIG. 46(b), the module 252a in the chip 250a shown in FIG. 46(a) has been changed without a test circuit added thereto. In other words, the module 252a is replaced by a module 252b (represented by Cxe2x80x2) changed from the module 252a, and an image of the module 252b is displayed. Further, the module 252b after changed is written as a data image 260b (represented by Cxe2x80x2) in the circuit information database 300.
Further, the chip 250a shown in FIG. 46(c) is in a state when the ECO design comes to an end. In the chip 250a, the module 252b is replaced by a module 252c (represented by Cxe2x80x3) obtained by changing the module 252b and adding a test circuit.
In this instance, the circuit of the module 252b includes a circuit same as the circuit of the module 252a before the addition of a test circuit and a circuit to which the change is added. When a test circuit is to be produced again for the module 252b, the designer designs so that the other portion than the changed portion may be the same as that of the circuit of the module 252a. Here, if the difference between the module 252a designed formerly and the module 252c designed using the ECO design is insignificant, then the designer may have to only design the portion to be changed also in layout design. Accordingly, the designer can shorten the time required for the design.
In the hierarchical design illustrated in FIGS. 44 to 46(c), the capacity of a database for a design scale in recent years is so great that it is difficult for a designing apparatus to load all data into a working memory. In order to prevent such shortage of the memory, when a designing apparatus for collective design is used, a designer produces circuit data as a black box in advance. Therefore, a complicated repetitive procedure is required.
Meanwhile, also where a designer uses a designing apparatus for division design, if the designing apparatus does not have a function of managing information regarding any portion which is not processed by the designing apparatus, the designer must correctly recognize any portion to be processed and must know information of any relating portion in addition to the portion to be processed. In addition, the designer must individually designate information other than information of the portion to be processed and must provide relating information to the designing apparatus for division design.
Here, if the design information is not referred to, then there is the possibility that, in the ECO design, a peculiar name different from the peculiar name in the ordinary design (refer to FIG. 8 which is hereinafter described) may be applied, and when peculiar names and design information are contrasted in a succeeding process, the name may be found to be incoincident.
Further, in conventional ECO design, a circuit is restored while an old circuit and a new circuit are compared with each other. Since the ECO design involves comparison between and differential analysis of circuits, complicated processing is required and this imposes a cumbersome operation upon the designer itself in designation of information and so forth.
Now, timing distribution in system design such as design of equipments as a system circuit or design of an apparatus is described with reference to FIGS. 47 to 49. In system design, timing distribution including PCB (Printed Circuit Board) design and LSI (Large Scale Integration) design is designed.
FIG. 47 is a schematic view illustrating timing distribution. Referring to FIG. 47, a pair of PCBs 140a and 140c are connected to the opposite ends of a PCB 140b through connector pins not shown. The PCBs 140a and 140c have LSIs 240 and 241 thereon, respectively. Here, the timing distribution signifies distribution of time required for transmission of a signal from the LSI 240 to the LSI 241, and the designer examines how long transmission time should be allocated between the PCBs 140a and 140c. The position at which an LSI is placed on a PCB is examined based on conditions called setup condition and hold condition. Here, the setup condition signifies a condition in which the propagation time of a signal remains within a predetermined time, and the hold condition is a condition for causing data and a clock for the data to coincide accurately with each other.
For example, if the LSI 240 on the PCB 140a is placed remotely from the LSI 241 on the PCB 140c, then the wiring line becomes long and causes signal delay. The signal delay is influenced for the worse by an excessively short wiring line as it comes far away from the hold condition. Accordingly, the delay time must be examined for both of a case wherein the LSI 240 and the LSI 241 are moved toward each other and another case wherein the LSI 240 and the LSI 241 are moved away from each other, and the specifications for distribution of the delay time are called timing specifications.
In FIG. 47, reference symbol a denotes a negative slack, and c denotes a positive slack. Thus, requesting information to request for distribution of a distribution value is transmitted from the negative slack a side to the positive slack c side.
In a conventional design flow for timing distribution, after an initial architecture of a system is examined, division of a PCB and an LSI is performed and timing specifications are set as constraint conditions. Then, designing and mounting (hereinafter referred to as implementing) of the inside of the LSI and so forth of a hierarchically lower layer are performed.
In the examination of such timing specifications, specifications called AC (Alternative Current) specification which prescribe a relationship between clocks and data are designed, and the inside of the LSI and so forth are implemented so as to satisfy the specifications. The result of the implementing, however, does not sometimes satisfy the timing specifications, and it is significant to discriminate limit values to the timing specifications.
FIG. 48 is a flow chart illustrating an outline of apparatus design. Referring to FIG. 48, apparatus specifications are examined first in step W1, and then architecture is designed in step W2. Then in step W3, circuit functions are allocated to PCBs or LSIs so that division design is performed.
If a PCB is selected in step W3, then PCB design is started in step W4. Thus, logic design, timing design, waveform analysis, mounting design and heat design are performed. Then, the PCB is implemented in step W5. On the other hand, if an LSI is selected in step W3, then LSI design is started in step W6. Thus, logical design, timing design, layout design, and power consumption analysis are performed. Then, the LSI is implemented in step W7.
FIG. 49 is a flow chart illustrating timing design. First, specifications of a system are determined in step W50, and then system architecture is examined in step W51, whereafter division of a PCB/LSI is examined in step W52.
In step W53, timing specifications of the PCB are examined, and the PCB is implemented in step W54. On the other hand, in step W55, timing specifications of the LSI are examined, and the LSI is implemented in step W56.
The steps of implementing the LSI and the PCB separately from each other use STA (Static Timing Analysis). The STA allows static timing verification without production of a simulation pattern.
It is to be noted that timing distribution is disclosed in the following known documents.
Japanese Patent Laid-Open (Kokai) HEI 5-181929 (hereinafter referred to as document 1) proposes a technique wherein, upon delay verification of hierarchical logic circuits, delay verification of a logic circuit of a higher hierarchical layer can be performed even if design or delay verification of another logic circuit of a lower hierarchical layer is not completed. The document 1 discloses a delay time verification system for hierarchical timing distribution of circuit blocks.
Japanese Patent Laid-Open (Kokai) HEI 9-212533 (hereinafter referred to as document 2) proposes a technique wherein, upon optimization of hierarchically designed hardware for each hierarchical layer, delay constraints to a critical path extending between different hierarchical layers are distributed appropriately for each hierarchical layer to optimize the delay efficiently. The document 2 discloses a method of optimizing distribution. It is to be noted that the critical portion signifies a portion which does not allow any delay and makes it impossible to allocate timings appropriately if delay occurs with the portion.
Delay distribution is performed efficiently using the techniques disclosed in the documents 1 and 2.
The conventional techniques, however, have a subject to be solved in that many items must be manually inputted by a designer, which results in a complicated designing procedure, an increased burden to the designer and a cause of occurrence of an error.
Besides, when a circuit whose design is completed once by a designer is to be changed, since the change adds or deletes an external terminal, incoincidence in terminal configuration sometimes occurs between higher and lower hierarchical layers. Accordingly, the conventional designing techniques have another subject to be solved in that, if such terminal configurations do not coincide with each other, mismatching occurs between the higher and lower hierarchical layers and is recognized as an error, which deteriorates the designing efficiency significantly.
Further, for timing distribution, the designer makes a trial many times with the value changed in architecture design examination. Accordingly, the designer cannot definitely know detailed timings until settled values of the object PCB or LSI are mapped from a library to the object circuit. Further, the designer allocates a predetermined delay value to the PCB or LSI once and examines the other necessary items.
Therefore, the conventional techniques have a further subject to be solved in that, in a step in which the designer cannot directly observe a circuit element such as a flip-flop, timing distribution of the entire system includes many unsettled portions and the timings of the entire system cannot be determined and therefore a change of a timing cannot be flexibly coped with.
In addition, circuit blocks each composed of LSIs, PCBs and so forth are not closely associated with each other. Further, in order to calculate an estimate of a latency (time necessary for processing) value or a delay value of a circuit block having a circuit element, the designer must actually perform implementing design. In contrast, in a critical portion (portion which does not allow delay), the association between architecture determination and an actual implementing step is weak. Therefore, the conventional techniques have a still further subject to be solved in that it is difficult to particularly examine an architecture and take over a floor plan between physical layers (for example, a floor plan from a PCB to an LSI) to another circuit block.
Further, deep sub-micron LSI design has proceeded, and the ratio at which the wiring line occupies has become more significant than the gate delay. Thus, the influence of the wiring line delay, particularly the delay at a global wiring line, is increasing.
Further, as a technique for laying a wiring line between pins arranged, a technique based on the Manhattan length is available, and a wiring line length is calculated simply and at a high speed using the technique. FIG. 50 is a diagrammatic view illustrating the Manhattan length. Referring to FIG. 50, a circuit module 170 shown includes a pair of circuit modules I51 and I50 which are connected to each other by a pair of paths L1 and L2. The two paths L1 and L2 correspond each to the Manhattan length and represent a right angle distance between the two points.
However, the techniques described are poor in accuracy at a place where wiring lines are located densely, and are low in processing speed in actual wiring. Particularly, such situations as described in (1-1) to (1-13) below occur.
(1-1) When the designer implements based on determined specifications, it is difficult for the designer to discriminate whether or not the specifications or the floor plan are good, and if timings distributed in accordance with the specifications suffer from some offset, then the design becomes impossible or a redundant circuit or circuits for adjusting the timings are required.
(1-2) Where a plurality of designers parallelly perform distributed design based on specifications of a design object, it is difficult for each designer to grasp, upon designing by itself, timing distribution of a higher layer or a lower layer, and consequently, timing distribution and verification of the entire system formed from PCBs or LSIs is difficult.
(1-3) When the designer implements, if the timing specifications are not satisfied, then the designer must negotiate for change of the specifications with another designer who is influenced by the change, and if the specifications cannot be changed, the higher architecture must be changed, which increases the design period significantly.
(1-4) Tolerances of used parts or circuit blocks defined in the timing library are different from each other. Accordingly, where a plurality of parts are designed in combination, a part of lower accuracy has an influence on a location at which another part of higher accuracy is used, and the designer cannot grasp the timing at the location accurately.
(1-5) Since the wiring line using the Manhattan length does not take an oblique wiring line on a PCB, a significant difference from a delay of an actual wiring line appears.
(1-6) Where wiring lines are located densely, a great error occurs between a wiring line delay value calculated based on the Manhattan length and a delay value of an actual wiring line, and a timing error is likely to occur.
(1-7) A logic designer cannot know it until a layout result comes out in what distance relationship wiring lines are located from transmission side pins to reception side pins in a netlist represented by a circuit diagram or a source code.
(1-8) Upon division examination of an LSI and a PCB, when it is examined whether a signal should be transmitted using a wiring line on the PCB or a module should be arranged in the inside of the LSI, a large number of man-hours are required for discrimination with the technology changed over between the PCB technology and the LSI technology. Further, upon designing through taking over from a floor plan of a PCB to a floor plan of an LSI, the designer must use a floor plan tool for exclusive use for an LSI to input the floor plan again, which requires a large number of man-hours.
(1-9) Upon examination of specifications, it is difficult for the designer to discriminate whether provisional wiring is used or actual wiring is used as wiring for each network.
(1-10) It is difficult to grasp the number of necessary wiring layers.
(1-11) Since an increased number of pins are required for an LSI, a great number of man-hours are required for distribution of timings for individual pins.
(1-12) In a design step of a PCB architecture, the designer cannot perform waveform analysis before completion of an LSI.
(1-13) In an architecture design step, the designer cannot examine whether or not a signal between blocks can be transmitted in one clock due to an influence of wiring line delay.
Further, although the advancing direction of the flow chart shown in FIG. 49 is one direction, the design step needs to be changed flexibly also from the fact that timing distribution is determined in an architecture design step.
It is an object of the present invention to provide a circuit designing apparatus wherein, in hierarchical design and ECO design for processing of a large scale circuit, information of units to be processed, terminal information, and change information of changes performed by the designing apparatus are stored and used to associate the units to be processed with each other to automatically produce, regenerate or optimize a desired circuit.
It is another object of the present invention to provide a circuit designing method and a timing distribution apparatus wherein, in timing distribution of LSIs or PCBs upon design of a system circuit, iterations in a downstream step are decreased to allow reduction of the designing period and augmentation in quality through timing distribution and timing verification performed with a floor plan taken into consideration in an upstream step and, when a circuit is changed by a designer, another designer can refer to contents of the change.
In order to attain the objects described above, according to an aspect of the present invention, there is provided a circuit designing apparatus, comprising a circuit information database for storing information regarding a circuit, a designing processing section for reading out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database for storing design information, obtained by the designing processing section, including at least peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit.
With the circuit designing apparatus, the used amount of a working memory is optimized and the burden to a designer upon hierarchical design or ECO design can be reduced to a level equal to that upon collective design. Further, continuous processing by full automation can be achieved, and consequently, reduction in processing time and hence in design period can be achieved.
The designing processing section may include a peculiarizing processing section for reading out the peculiarizing information from the design information database and applying different names with each other to the individual units to be processed, a test circuit production processing section for reading out the change history information from the design information database and producing a test circuit of a higher hierarchical layer, and a load adjustment processing section for reading out the terminal load and driving capacity information from the design information database, applying the design information to terminals included in a circuit of the higher hierarchical layer and adjusting the load based on the design information.
The circuit designing apparatus is advantageous in that design information such as boundary information of hierarchical layers and terminal information is inputted automatically, and a processing object portion in the current processing is automatically discriminated from the processing history. The circuit designing apparatus is advantageous also in that design information included in a portion other than the processing object can be extracted automatically and utilized for the processing of the portion being currently designed.
According to another aspect of the present invention, there is provided a circuit designing method, comprising a processing production step of producing, by means of a designing processing section for reading out information regarding a circuit from a circuit information database which stores information regarding the circuit and designing the circuit for each predetermined unit to be processed, first unit information which relates to a processing result of a first unit obtained by processing the first unit, a design information collection step of collecting design information including at least peculiarizing information of circuit elements, the design information being produced in the processing production step, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit, a design information writing step of writing the design information collected in the design information collection step for each unit to be processed into a design information database connected to the design processing section for storing the design information, a reference step of referring to the design information regarding the first unit in order to process a second unit based on the design information written in the design information writing step, a recognition step of recognizing a reference relationship regarding the design information relating to the first unit referred to in the reference step, a circuit information database reference step of referring to unit information regarding a position and a result of the processing stored in the circuit information database based on the reference relationship obtained in the reference step, and a circuit information database writing step of updating the circuit data obtained after a design processing.
With the circuit designing method, reading out of information regarding a lower hierarchical layer from the circuit information database is unnecessary. Therefore, the capacity of the working memory and so forth can be saved significantly.
According to a further aspect of the present invention, there is provided a timing distribution apparatus for use for hierarchical design, comprising plurality of timing distribution production sections individually provided corresponding to a plurality of design hierarchical layers for receiving block information regarding a function of a circuit from a plurality of timing information databases having netlist information regarding a wiring line scheme and outputting timing distribution values obtained by distributing a delay value produced by a delay element of the circuit, and an inter-hierarchical layer association manager for dynamically changing connections between the plurality of timing distribution production sections and transmitting and receiving modification information regarding the timing distribution values to and from the plurality of timing distribution production sections.
With the timing distribution apparatus, when the timing specifications are changed, a range of the influence of the change can be referred to immediately, and consequently, a reference mistake upon such change of the specifications is eliminated. Further, the combination of provisional wiring and actual wiring can achieve both of augmentation of an execution speed of floor planning and augmentation of an accuracy. Furthermore, a hierarchical entity can be used and a distributed design environment can be constructed. Further, in top-down design, only a necessary portion can be particularized, and it can be examined whether or not timing specifications divided by trial and examination by one design team. Consequently, problems upon implementing can be estimated and otherwise possible iterations can be reduced.
The circuit designing apparatus may be constructed such that the timing distribution production sections is formed as agents individually provided corresponding to the plurality of design hierarchical layers and having a hierarchical layer entity having design information and program data for processing the design information, and the inter-hierarchical layer association manager is formed as a manager connected to the timing distribution production sections as the agents for transmitting and receiving information regarding the timing distribution values individually to and from the plurality of design hierarchical layers.
With the timing distribution apparatus, when a timing-driven layout process which uses logic design and physical layout in combination is performed with an object-oriented hierarchical entity, timings between logic layers and a physical layer can be determined definitely and can be associated with each other readily.
In the timing distribution apparatus, the plurality of design hierarchical layers can communicate with each other through the inter-hierarchical layer association manager.
Any one of the peculiarizing processing section, test circuit production processing section and load adjustment processing section may perform hierarchical design wherein the circuit is designed in a state wherein one of the units to be processed hierarchically contains another unit designed independently. This makes it possible to design a large scale circuit for each part.
The peculiarizing processing section may includes a peculiar name application rule setting section and a peculiar name production section. With the circuit designing apparatus, a new name is produced based on an original peculiar name before a circuit change by a designer and a set value set by the designer, and even if a plurality of new names are produced by reference to the peculiar name by a plural number of times, the names can be discriminated definitely from one another and the designer can group the names readily and particularly for each unit to be processed. Further, otherwise possible overlapping between the names of units processed and the name of a unit being currently processed.
The circuit designing apparatus may be constructed such that the peculiarizing processing section further includes a plural-reference analysis section for searching for a location at which a plurality of same circuit units are used and discriminating a hierarchical layer, a cell and a black box regarding a type of the circuit units at the location, and the peculiar name production section produces a peculiar name for each of the plural-reference units and single-reference units discriminated by the plural-reference analysis section. The peculiarizing processing section may further include a circuit data duplication section for allocating peculiar names produced by the peculiar name production section to the plural-reference units and the single-reference units to duplicate the circuit data. With the circuit designing apparatus, the peculiarizing processing can be performed efficiently, and fine design can be achieved.
Any of the peculiarizing processing section, test circuit production processing section and load adjustment processing section may include a processing object discrimination section for discriminating, when the higher hierarchical layer is to be processed, whether or not the unit to be processed is an object of processing based on the design information written in the design information database, and a processing data acquisition section for acquiring circuit data of the unit to be processed from the circuit information database based on a discrimination by the processing object discrimination section of whether or not the unit to be processed is an object processed. This makes it possible to save the working memory.
Any of the peculiarizing processing section, test circuit production processing section and load adjustment processing section may include a processing object discrimination section for discriminating based on the design information written in the design information database whether or not the unit to be processed is an object of the processing. This makes it possible to easily obtain information regarding a portion to be processed.
The processing object discrimination section may discriminate, based on first unit information which relates to a processing result of a first unit obtained by processing the first unit of the design information, whether or not a unit included in a second unit to be processed next has been processed already. This makes it possible to readily discriminate a location of an object to be processed.
The test circuit production processing section may include a hierarchical layer matching restoration section for eliminating terminal mismatching between a terminal added for receiving a test signal input in a lower hierarchical layer and a terminal in a layer referred to by a higher hierarchical layer. With the circuit designing apparatus, the operability of the designer in ECO design is augmented significantly.
Any of the peculiarizing processing section, test circuit production processing section and load adjustment processing section may perform engineering change order (ECO) design. This makes it possible to use the same operation procedure repetitively in design of a circuit.
The circuit designing apparatus may be constructed such that any of the peculiarizing processing section, test circuit production processing section and load adjustment processing section includes a design information read-in section for reading in normal design information produced upon normal design, and a processing object discrimination section for discriminating circuit data to be processed using the normal design information and engineering change order design object unit information given in the form of a parameter, and designs a circuit which is common to a circuit designed normally using the normal design information except a changed portion. With the circuit designing apparatus, continuous processing by full automation can be achieved, and consequently, reduction in processing time and hence in design period can be achieved.
The peculiarizing processing section may include a processing object discrimination section for discriminating based on the design information written in the design information database whether or not the unit to be processed is an object of processing, and a peculiar name production section for producing, when the processing object discrimination section discriminates that the unit to be processed is an object of processing, a peculiar name so as to establish a reference relationship same as the reference relationship stored in the design information database, but producing, when the processing object discrimination section discriminates that the unit to be processed is not an object of processing, a peculiar name different from the peculiar names allocated already. With the circuit designing apparatus, when the upper hierarchical layer refers to the design information, the unit to be processed can be duplicated by a number of times equal to the number of times of such reference, and a peculiar name which does not overlap with any other peculiar name can be applied to each of the units to be processed after the addition.
The test circuit production processing section may include a circuit analysis section for using the normal design information produced upon normal design with regard to an engineering change order design object unit and the test circuit rule, based on the design information database, to extract identification data for identification of a portion with regard to which a test circuit (same as that upon the normal design) can be produced and another portion with regard to which a new test circuit should be produced. This optimizes the used amount of the working memory.
The hierarchical layer matching restoration section may use the normal design information regarding normal design and the terminal information of the engineering chain order design object unit and the higher hierarchical layer from within the design information to restore the hierarchical layer matching. This makes it possible to design a large scale circuit for each part.
The test circuit production processing section may further include a test circuit production section for producing a test circuit which is the same in regard to a portion of the engineering change order design object unit with regard to which a test circuit same as that upon the normal design can be produced based on the identification data extracted by the circuit analysis section, but producing a test circuit conforming to the test circuit rule with regard to another portion of the engineering change order design object unit with regard to which a new test circuit should be produced. This significantly augments the design efficiency in ECO design.
The design information read-in section may make the hierarchical layer names before the peculiarizing and the hierarchical layer names after the peculiarizing correspond to each other so as to allow the circuit data after the peculiarizing to be referred to with the hierarchical layer names before the peculiarizing. With the circuit designing apparatus, information of whether or not peculiarizing processing has been performed and hierarchical layer names before and after such peculiarizing processing are obtained.
The load adjustment processing section may include a load analysis section for analyzing a terminal capacity which can be driven by a logic element to extract an undrivable terminal or terminals, and a circuit adjustment section for adjusting the driving capacity of the undrivable terminal or terminals extracted by the load analysis section. This makes it possible to adjust each terminal of the circuit so as to have an appropriate capacity.
The circuit information database may include a circuit information writing section for writing circuit information for each processed unit into the circuit information database in at least one of hierarchical design and engineering change order design, and a reference section connected to the circuit information writing section for referring to the circuit information written for each unit to be processed. This augments the design efficiency.
The design information database may include a plurality of storage sections for individually storing the circuit elements into individual files. With the circuit designing apparatus, the design information is reflected on circuit design, and the working efficiency in terms of the design period and so forth is augmented.
According to a still further aspect of the present invention, there is provided a circuit designing method, comprising a first processing step of processing a fourth unit which contains a third unit by means of a designing processing section for reading out information regarding a circuit from a circuit information database which stores information regarding the circuit and designing the circuit for each predetermined unit to be processed, a third unit information collection step of collecting third unit information regarding a processing result of the third unit being produced in the first processing step, a design information writing step of writing the third unit information collected in the third unit information collection step into a design information database connected to the design processing section for storing the design information, and a discrimination step of discriminating, based on the third unit information written in the design information writing step, whether or not a third processed unit obtained by changing the third unit contains a fourth processed unit obtained by changing the fourth unit and discriminating whether or not the third processed unit is equivalent to the third unit.
With the circuit designing method, continuous processing by full automation can be achieved, and consequently, reduction in processing time and hence in design period can be achieved. Further, hierarchical design can be realized readily, and besides, hierarchical design of a large scale circuit can be performed very efficiently.
According to a yet further aspect of the present invention, there is provided a computer-readable recording medium on which a program is recorded, the program causing a computer to function so as to read out information regarding a circuit from a circuit information database in which the information regarding the circuit is stored and design the circuit for each predetermined unit to be processed and then store design information obtained by the design and including at least peculiarizing information of a circuit element, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. With the program of the recording medium, an environment in which a large scale circuit is designed can be constructed simply and conveniently.
According to a yet further aspect of the present invention, there is provided a computer-readable recording medium on which a program is recorded, the program causing a computer to function so as to execute a processing production step of producing, by means of a designing processing section, first unit information which relates to a processing result of a first unit obtained by processing the first unit, a design information collection step of collecting design information including at least peculiarizing information of circuit elements being produced in the processing production step, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit, a design information writing step of writing the design information collected in the design information collection step for each unit to be processed into a design information database connected to the design processing section for storing the design information, a reference step of referring to the design information regarding the first unit in order to process a second unit based on the design information written in the design information writing step, a recognition step of recognizing a reference relationship regarding the design information relating to the first unit referred to by the reference step, a circuit information database reference step of referring to unit information regarding a position and a result of the processing stored in the circuit information database based on the reference relationship obtained in the reference step, and a circuit information database writing step of updating the circuit data obtained in the design processing. With the program of the recording medium, for example, when the first unit is contained in the second unit, it is automatically recognized whether or not the first unit has been processed already.
According to a yet further aspect of the present invention, there is provided a computer-readable recording medium on which a program is recorded, the program causing a computer to function so as to execute a first processing step of reading out information regarding a circuit from a circuit information database which stores information regarding the circuit and processing a fourth unit which contains a third unit by means of a designing processing section for designing the circuit for each predetermined unit to be processed, a third unit information collection step of collecting third unit information regarding a processing result of the third unit being produced in the first processing step, a design information writing step of writing the third unit information collected in the third unit information collection step into a design information database connected to the design processing section for storing the design information, and a discrimination step of discriminating, based on the third unit information written in the design information writing step, whether or not a third processed unit obtained by changing the third unit contains a fourth processed unit obtained by changing the fourth unit and discriminating whether or not the third processed unit is equivalent to the third unit. With the program of the recording medium, continuous processing by full automation can be achieved, and consequently, reduction in processing time and hence in design period can be achieved.
Each of the timing distribution production sections may include a logic/constraint information storage section for storing delay element information, a floor planning section connected to the logic/constraint information storage section for distributing timings based on a floor plan to perform provisional wiring line, a timing information storage section for storing the netlist information, and a distribution manager for outputting the delay value based on the netlist information. This makes flexible design change possible.
The floor planning section may include an arrangement processing section for presenting a portion with regard to which a distribution value as attribute information can be improved and modified based on a slack from the constraint information and storing arrangement information originating from the delay element information, an actual wiring and provisional wiring execution section for performing association with actual wiring and provisional wiring, and outputting wiring information, a wiring information storage section for storing the wiring information, a physical technology information storage section for storing physical technology information including delay values per unit length corresponding to wiring line layers and load capacities per unit length, and a conversion section for converting the wiring information into a delay value based on the delay length and the load capacity and outputting the delay value. With the timing distribution apparatus, a delay value can be calculated readily from a wiring line length.
The actual wiring and provisional wiring execution section may perform wiring using both of actual wiring which requires long calculation time and provisional wiring which requires short calculation time and extract the timing distribution values. With the timing distribution apparatus, the designer can examine timing specifications through provisional wiring and perform actual wiring with the timing distribution changed based on a result of the examination.
The actual wiring and provisional wiring execution section may include a Manhattan length provisional wiring section for performing Manhattan length provisional wiring for both of a PCB and an LSI, an oblique Manhattan length provisional wiring section for performing provisional wiring using oblique wiring wherein a wiring line is located obliquely, and an actual wiring association section for performing wiring for the printed circuit board and the large scale integrated circuit. This augments the efficiency of the wiring operation.
The actual wiring and provisional wiring execution section may perform the provisional wiring based on the Manhattan length provisional wiring, the oblique Manhattan length provisional wiring and the actual wiring. This augments the accuracy also where the wiring line congestion degree is high.
The actual wiring and provisional wiring execution section may read out the delay values and the load capacities of a selected hierarchical layer from the physical technology information storage section, vary the delay time per unit wiring line length and distribute the delay time. This augments the efficiency of the wiring.
The actual wiring and provisional wiring execution section may perform actual wiring based on a margin calculated with regard to the timing distribution value obtained by the provisional wiring and a wiring line congestion degree representative of the density of the wiring lines. With the timing distribution apparatus, since provisional wiring or actual wiring is switchably used automatically in response to the wiring line congestion degree, the trade-off can be utilized effectively, and the time and labor of the designer can be reduced.
The actual wiring and provisional wiring execution section may output information for analysis regarding information which is insufficient in the actual wiring so as to allow cooperation with another designing apparatus which uses another computer which can perform only the actual wiring. With the timing distribution apparatus, information which is insufficient upon actual wiring is conveyed to the designer, and the designer can produce information necessary for analysis based on the information and transmit the information to a layout CAD apparatus for exclusive use for actual wiring so that the layout CAD apparatus may perform actual wiring.
The actual wiring and provisional wiring execution section may perform the provisional wiring and the actual wiring based on a region in which wiring is inhibited and the wiring line congestion degree. With the timing distribution apparatus, provisional wiring lines and detailed actual wiring lines which rely upon circuit blocks of an object of design can be located in a mixed state, and distribution values of timings can be extracted.
The actual wiring and provisional wiring execution section may discriminate based on a clock frequency used as a constraint condition whether or not arrival within time within which arrival is essentially required is possible and issue, if the arrival is impossible, an instruction to insert at least one of a buffer and a flip-flop into the netlist information between a plurality of circuit blocks. With the timing distribution apparatus, since a buffer or the like is inserted only when arrival at a virtual pin is impossible, the constraint condition can be satisfied efficiently.
The actual wiring and provisional wiring execution section may arrange terminals included in circuit blocks based on the constraint information. This makes arrangement simple and easy.
The inter-hierarchical layer association manager may extract a circuit block whose timing information data is insufficient and inputs the extracted circuit block to the timing information database, and notify a designer of the circuit block whose timing information data is insufficient. This augments the design efficiency of the designer.
The timing distribution apparatus may be constructed such that the floor planning section can change a wiring line width in a circuit block while the actual wiring or the provisional wiring is proceeding. This makes designing of a circuit flexible.
The timing distribution apparatus may be constructed such that the inter-hierarchical layer association manager can change the combination of the plurality of distribution managers. With the timing distribution apparatus, the combination of distribution manages can be changed freely and dynamically in response to a design object.
Each of the timing distribution production sections may further include a waveform analysis information production section for producing information for waveform analysis of a PCB from I/O buffer information of a hierarchical layer of an LSI. This makes it possible to analyze a waveform simply and readily.
Each of the timing distribution production sections may output the timing distribution value based on another timing specification set in advance and the timing distributed by the floor planning section. This makes it possible for the designer to refer to a distribution report on which the distribution value is described.
The timing distribution apparatus may be constructed such that the floor planning section can change a scale or a shape of the circuit blocks while the actual wiring or the provisional wiring is proceeding. This makes flexible arrangement design possible.
Each of the timing distribution production sections may read in timing distribution values back annotated from logical design or layout examination using the source code. This makes it possible for the designer to perform a simulation readily.
Each of the timing distribution production sections may further include an annotator for writing information arising from the timing distribution values into the source code. This makes the user interface between the designer and the circuit designing apparatus closer.
The annotator may write netlist information regarding a wiring scheme into the source code. With the timing distribution apparatus, a distributed value is back annotated into the source code, and a delay value is automatically set or changed.
The physical technology information storage section may store the wiring line length and the delay value per unit length and load capacity per unit length in a mutually associated relationship. With the timing distribution apparatus, a delay value is calculated from a wiring line length.
The inter-hierarchical layer association manager may receive a timing distribution specification changing request transmitted from one of the plurality of timing information databases, extract any of the other timing information databases on which the timing distribution specification change may possibly have an influence, and inquire the pertaining timing information database for whether or not change of the timing distribution values is permissible. With the timing distribution apparatus, a change of timing specifications can be conveyed readily.
The inter-hierarchical layer association manager may output, when a response representing that change of the timing distribution values is permissible is received from the pertaining timing information database, to the one timing information database a notification that change of the timing distribution values is permissible. Also this allows the timing specifications to be changed rapidly.
The inter-hierarchical layer association manager may update, when the timing distribution values are changed, a higher hierarchical layer entity than the hierarchical layer in which the timing distribution values are changed. Also this allows the timing specifications to be changed rapidly.
The distribution manager may includes a distribution editor connected to the logic/constraint information storage section for distributing timings, a database reference registration section connected to the distribution editor, the logic/constraint information storage section and the timing information storage section for outputting the netlist information, a self hierarchical layer TDB outputting and other hierarchical layer TDB reflection section for inputting and outputting timing distribution information of a hierarchical layer to which the distribution manager belongs and timing distribution information of the other hierarchical layer or layers, and an arbitration control section for performing arbitration. With the timing distribution apparatus, a distribution value is reflected efficiently.
The distribution manager calculates a skew based on one or those of wiring line paths of netlist information regarding a wiring scheme which are other than a common wiring line path or paths. With the timing distribution apparatus, calculation with a dispersion of a common portion removed can be performed automatically.
The distribution manager may apply a name representative of a wiring line scheme as a sub signal name to each of the wiring line paths. This eliminates the necessity for re-layout and allows the designer to know the number of wiring line layers, and besides decreases the man-hour for distribution.
The distribution manager may apply a sub signal name in an associated relationship with a fan-out number. With the timing distribution apparatus, since an attribute is provided to each of pins and wiring lines, the man-hour decreases as well.
The distribution manager may display a gradation of a wired portion corresponding to the value of the constraint information in color on an operation screen. This makes it possible to eliminate a dispersion of a common portion.
The distribution manager may display the timing distribution values and a range in value within which the timing can be distributed on a figure which shows the circuit blocks. With the timing distribution apparatus, the designer can design a circuit of a high degree of reliability.
According to a yet further aspect of the present invention, there is provided a computer-readable recording medium on which a program is recorded, the program causing a computer to function as a plurality of timing distribution production sections and an inter-hierarchical layer association manager. Thus, for example, boundary information of terminals and design information of the terminals and so forth are automatically inputted, and a portion other than a processing object in current processing is automatically discriminated from history information. Further, design information of the portion other than the processing object is automatically extracted and used for processing of a portion being currently designed. Further, since a wiring scheme for a critical portion can be designated before layout, wiring having a high degree of reliability after actual layout can be achieved. Since an existing PCB layout CAD apparatus or an existing LSI layout CAD apparatus can be used for detailed examination and implementing can be performed immediately, design can be proceeded without changing an existing design flow. In addition, since waveform analysis of a PCB can be performed based on information for waveform analysis before completion of an LSI, parallel designing of the LSI and the PCB is facilitated.
Further, since re-utilization of floor plan information which does not rely upon the technology can be achieved, existing layout resources can be utilized efficiently. Further, timing design for a combination of a PCB and an LSI which are components of a high speed system which is considered to become significant more and more in the future can be anticipated. Further, in architecture design, a portion which is critical and has significant timing specifications upon implementing can be grasped in advance through distributed examination, which allows significant reduction of the period of development and high reliability design.
The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements denoted by like reference symbols.